|
|
72.
|
|
|
output register of preceding `movprfx' used as input
|
|
|
|
|
(no translation yet)
|
|
|
|
Located in
aarch64-opc.c:6548
|
|
|
73.
|
|
|
register size not compatible with previous `movprfx'
|
|
|
|
|
(no translation yet)
|
|
|
|
Located in
aarch64-opc.c:6564
|
|
|
74.
|
|
|
branch operand unaligned
|
|
|
|
|
operando de ramificación sin alinear
|
|
Translated and reviewed by
Paco Molinero
|
|
|
|
Located in
alpha-opc.c:154
|
|
|
75.
|
|
|
jump hint unaligned
|
|
|
|
|
omite pista sin alinear
|
|
Translated by
Fco. Javier Serrador
|
|
|
|
Located in
alpha-opc.c:170 alpha-opc.c:186
|
|
|
76.
|
|
|
Warning: disassembly may be wrong due to guessed opcode class choice.
Use -M<class[,class]> to select the correct opcode class(es).
[tab][tab][tab][tab] |
|
|
[tab] represents a tab character.
Please write it exactly the same way, [tab], in your
translation.
|
|
|
represents a line break.
Start a new line in the equivalent position in the translation.
|
|
|
|
|
Aviso: desensemblado quizá está equivocado debido a clase de opcode adivinadas elegidas.
Utilice .M<class[,class]> para seleccionar la clase correcta de código de operación.
[tab][tab][tab][tab] |
|
Translated by
Fco. Javier Serrador
|
|
|
|
Located in
arc-dis.c:380
|
|
|
77.
|
|
|
An error occurred while generating the extension instruction operations
|
|
|
|
|
(no translation yet)
|
|
|
|
Located in
arc-dis.c:442
|
|
|
78.
|
|
|
unrecognised disassembler CPU option: %s
|
|
|
|
|
(no translation yet)
|
|
|
|
Located in
arc-dis.c:850
|
|
|
79.
|
|
|
Warning: illegal use of double register pair.
|
|
|
represents a line break.
Start a new line in the equivalent position in the translation.
|
|
|
|
|
(no translation yet)
|
|
|
|
Located in
arc-dis.c:1323
|
|
|
80.
|
|
|
Enforce the designated architecture while decoding.
|
|
|
|
|
(no translation yet)
|
|
|
|
Located in
arc-dis.c:1489
|
|
|
81.
|
|
|
Recognize DSP instructions.
|
|
|
|
|
(no translation yet)
|
|
|
|
Located in
arc-dis.c:1491
|
